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    • 专利摘要:
    A method of designing a phase locked loop, of the type comprising; - a controlled frequency oscillator (VCO); a phase comparator (CMP), configured to determine a phase difference between an output signal of said controlled frequency oscillator and a reference signal; a corrector (F1), said first corrector, configured to receive as input a signal representative of said phase difference and to generate at its output a signal called said first correction signal; at least one other corrector (F2), said second corrector, configured to receive as input a signal representative of or affected by a phase noise of said reference signal or of said output signal of said controlled frequency oscillator and to generate at its output a signal said second correction signal; and - means (NA) for generating a servo signal (u) of said controlled frequency oscillator from said first and second correction signals; said method using the H-infinite method. A method of manufacturing such a loop comprising a design step implementing this method. Phase lock loop thus obtained.
    公开号:FR3025911A1
    申请号:FR1458667
    申请日:2014-09-15
    公开日:2016-03-18
    发明作者:Michael Pelissier；Anton Korniienko；Mykhailo Zarudniev；Gerard Scorletti；Olesia Mokrenko；Eric Blanco；Patrick Villard；Gerard Billiot
    申请人:Centre National de la Recherche Scientifique CNRS；Universite Claude Bernard Lyon 1 UCBL；Commissariat a lEnergie Atomique CEA；Ecole Centrale de Lyon；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] The invention relates to a phase-locked loop, to methods of designing and manufacturing such phase-locked loops and to a receiver with a phase-locked loop, and to a method for designing and manufacturing such phase-locked loops and to a receiver with a phase-locked loop. radio frequency comprising such a phase locked loop. The phase locked loop (PLL) is a well-known electronic circuit in itself, including a controlled frequency oscillator (usually a voltage controlled oscillator, or VCO of English). Voltage Controlled Oscillator ") and a corrector, or controller, in a closed loop generating a control signal of said oscillator to slave its output signal to a reference signal (the corrector is also called" filter "because in the simplest embodiments it is a low-pass filter). It is used in particular to produce frequency synthesizers; indeed, by introducing a frequency divider in the feedback loop of the corrector, a VCO output signal is obtained at a frequency that is a multiple of the reference signal, generated for example by a quartz oscillator. The output signal of the VCO (and therefore of the PLL) is inevitably affected by a phase noise, which has multiple origins. The main sources of phase noise are the reference oscillator, generating the reference signal, and the frequency controlled oscillator. The corrector is generally designed to minimize the influence of these noise sources in the operating spectral band of the phase-locked loop, that is, to reject phase noise in a frequency band. given. As will be explained in more detail below, however, in a known phase lock loop of the prior art there is a fundamental limit to rejection of the phase noise. More specifically, it is possible to demonstrate that the corrector can not efficiently filter, at the same frequency, the reference phase noise and that due to the VCO. To obtain an output signal with low phase noise despite this intrinsic limitation, it is necessary to use VCOs and reference oscillators of very high quality - and therefore expensive - and difficult to integrate on. silicon technologies and / or high order correctors. Even with these precautions, the intrinsic limitations of the conventional phase-locked loop architecture preclude sufficiently effective noise filtering for some applications. The aim of the invention is to remedy this drawback of the prior art and to provide a phase-locked loop having a better rejection of the phase noise without necessarily having to use very high quality VCOs and reference oscillators. or a high order corrector. According to the invention, such a goal is achieved through a phase locked loop, or PLL, "with multiple degrees of freedom". By this is meant a PLL comprising at least two correctors having linearly independent input signals. It should be understood that these correctors can be realized in the form of a single physical device, but having at least two inputs, at least one output and two linearly independent input / output (transfer functions). Documents [ChM-2007] and [SNI-2012] disclose PLLs that can be considered "two degrees of freedom". In the case of the document [ChM-2007], a conventional type PLL is modified by the addition of a signal path realizing a feed-forward ("feed-forward") in order to increase the speed loop response. This signal path 25 has a constant gain as a function of frequency, which allows no improvement in phase noise rejection performance. The possibility of using a corrector in advance control having a variable gain depending on the frequency is mentioned, but no method of designing such a corrector is mentioned. Furthermore, the document does not suggest that such a corrector could be used to reduce the phase noise of the output signal.
    [0002] The document [SNI-2012] also discloses a PLL comprising, in addition to a conventional corrector, a signal path carrying out an anticipatory command. The latter includes a frequency estimator followed by a low-pass filter. In this case, either, there is no question of improving the rejection of the phase noise, but only of increasing the speed of synchronization and of ensuring the stability of the phase-locked loop. An object of the invention for achieving the above-mentioned purpose is a method of designing a phase lock loop, of the type comprising; a controlled frequency oscillator; a phase comparator, configured to determine a phase difference between an output signal of said controlled frequency oscillator and a reference signal; A corrector, said first corrector, configured to receive as input a signal representative of said phase difference and to generate at its output a signal called said first correction signal; at least one other corrector, called the second corrector, configured to receive as input a signal representative of or affected by a phase noise of said reference signal or of said output signal of said controlled frequency oscillator and to generate at its output a signal said second correction signal; and - means for generating a servo signal of said frequency controlled oscillator from said first and second correction signals; said method comprising a step of determining transfer functions of said correctors and being characterized in that said step is implemented, by means of a computer, by applying the method H_ using: - at the input, a function of weighting of a phase noise of said controlled frequency oscillator, said first weighting function, and a weighting function of a phase noise of a reference signal, referred to as the second weighting function, determined from densities nominal power spectra of said noise; and at the output, at least one weighting function of a phase noise of an output signal of the phase-locked loop or a tracking error of said reference signal, referred to as the third weighting function, determined from a phase noise power spectral density mask of said output signal to be complied with. According to various embodiments of such a method: Said step of determining transfer functions of said correctors can comprise the following sub-steps: a) determining a nominal power spectral density of said reference signal; b) determining a nominal power spectral density of the phase noise of said controlled frequency oscillator; C) determining a phase noise power spectral density mask of said output signal to be complied with; d) from said nominal power spectral densities and said power spectral density mask, determining at least said first, second and third weighting functions; E) construct an augmented system of said weights; and f) applying the method H_ to said augmented system to synthesize the transfer functions of said correctors. Said step d) may also comprise the determination of an output weighting function, called the fourth weighting function, of the power spectral density of said servocontrol signal from a spectral power density mask of said signal enslavement to be respected. The method may also comprise a sub-step d) of simplifying the weighting functions determined during sub-step d), the weighting functions thus simplified being used during said sub-step e), said simplification being implementation by approximating said weighting functions with lower order and lower modulus transfer functions at least over a spectral operating range of the phase locked loop. The method may also comprise a sub-step g) of simplification of the transfer functions synthesized during said sub-step f), said simplification being implemented by approaching said transfer functions by more order transfer functions. low. Said step f) can be implemented with an additional constraint, according to which the modulus of the transfer function between said output signal of said controlled frequency oscillator and said reference signal has, in at least one spectral range, a slope greater than or equal to +20 dB / decade and preferably 40 dB / decade. Said phase-locked loop may comprise at least one other corrector, called the third corrector, configured to receive as input a signal representative of or affected by a phase noise generated inside said loop, other than said noise of phase of said output signal of said controlled frequency oscillator, and for generating at its output a signal said third correction signal, said means for generating a servocontrol signal of said controlled frequency oscillator being configured to generate said servocontrol signal also from said third correction signal. said step of determining transfer functions of said correctors, implemented by said method Ho., also using a weighting function of said phase noise other than said phase noise of said output signal of said controlled frequency oscillator, also determined from the power spectral density of said noise. Another object of the invention is a method of manufacturing a phase-locked loop of the type comprising; a controlled frequency oscillator; a phase comparator for determining a phase difference between an output signal of said controlled frequency oscillator and a reference signal; A corrector, said first corrector, configured to receive at the input a signal representative of said phase difference and to generate at its output a signal called said first correction signal; at least one other corrector, called the second corrector, configured to receive as input a signal representative of or affected by a phase noise of said reference signal or of said output signal of said controlled frequency oscillator and to generate at its output a signal said second correction signal; and - means for generating a servo signal of said controlled frequency oscillator from said first and second correction signals; said method comprising: - a step of designing said phase locked loop; and a step of physically producing the phase lock loop thus conceived; characterized in that said design step is carried out by a method as defined above. Advantageously, said phase-locked loop may comprise at least one other corrector, called third corrector, configured to receive as input a signal representative of or affected by a phase noise generated inside said loop, other than said noise. phase of said output signal of said controlled frequency oscillator, and for generating at its output a signal said third correction signal, said means for generating a servo signal of said controlled frequency oscillator being configured to generate said signal of said also controlling from said third correction signal. Yet another object of the invention is a phase locked loop comprising: a controlled frequency oscillator; A phase comparator for determining a phase difference between an output signal of said controlled frequency oscillator and a reference signal; a corrector, said first corrector, configured to receive as input a signal representative of said phase difference and to generate at its output a signal said first correction signal; at least one other corrector, called the second corrector, configured to receive as input a signal representative of or affected by a phase noise of said reference signal or of said output signal of said controlled frequency oscillator and to generate at its output a signal said to be second correction signal; and - means for generating a servo signal of said controlled frequency oscillator from said first and second correction signals; Characterized in that said first and second corrector have non-constant transfer functions, selected so as to allow the rejection, in the same frequency band, of the phase noise of said reference signal and of the phase noise of said output signal said frequency controlled oscillator.
    [0003] According to various embodiments of such a phase-locked loop - said second corrector may be configured to receive as input: either a signal representative of the phase of said reference signal; an estimate of the phase noise of said reference signal. Said phase-locked loop may also comprise a circuit for determining an estimate of the phase noise of said reference signal comprising: a delay module, configured to generate a delayed version of a time Td of said reference signal; a phase shifter module, configured to generate a version of said reference signal having a phase shift Sy, with g ç a - COrefTd = -2 + 27rk, ke z, where COref is the frequency of said reference signal; and a mixer configured to input the output signals of said retarder and phase shifter modules and to output its product; said second corrector being configured to receive as input said estimate of the phase noise of said reference signal. Said second corrector may be configured to receive as input: a signal representative of the phase of said output signal of said controlled frequency oscillator; an estimate of the phase noise of said output signal of said controlled frequency oscillator. Said phase-locked loop may also include a circuit for determining an estimate of the phase noise of said output signal comprising: a delay module, configured to generate a delayed version of a time Td of said output signal; a phase shifter module, configured to generate a version of said output signal having a phase shift,, with-co o o - 77 77 77 77 77 77 77 77 77 où où où où où où où où où où, where a), is the frequency of said output signal; and a mixer configured to receive as input the output signals of said delay and phase shifter modules and to output its product; said second corrector being configured to receive as input said estimate of the phase noise of said output signal. Said phase-locked loop may also comprise at least one other corrector, called the third corrector, configured to receive as input: a signal representative of or affected by a phase noise generated inside said loop, other than said phase noise of said output signal of said controlled frequency oscillator, and for generating at its output a signal said third correction signal, said means for generating a servo signal of said controlled frequency oscillator being configured to generate said servo signal also from said third correction signal. Yet another object of the invention is a radio frequency reception chain comprising: a radio frequency preamplifier; a mixer configured to receive an input of an output of said radio frequency preamplifier and a sinusoidal frequency conversion signal, and to output an intermediate frequency signal; and a circuit for generating said sinusoidal frequency conversion signal; wherein said generating circuit of said sinusoidal frequency conversion signal comprises such a phase locked loop, using said mixer as a mixer of said phase noise estimate determining circuit of said output signal, and an oscillator configured to generate said reference signal. Other characteristics, details and advantages of the invention will emerge on reading the description given with reference to the appended drawings given by way of example and which represent, respectively: FIGS. 1 and 2, two representations of a functional diagram of a PLL "with a degree of freedom" known from the prior art; FIG. 3, a graph for understanding why a PLL of the type of FIGS. 1 and 2 can not efficiently filter all contributions to the phase noise of its output signal; FIGS. 4a and 4b, the functional diagrams of two variants of a PLL "with two degrees of freedom" according to a first embodiment of the invention using a second corrector in anticipation control mode ("feed forward" in English) FIGS. 5a and 5b, the functional diagrams of two variants of a "two-degree of freedom" PLL according to a second embodiment of the invention using a second corrector in a feedback mode; FIGS. 6a, 6b and 7, frequency masks serving as input data of a design method according to an embodiment of the invention; FIGS. 8 and 9, constraints on the closed loop transfer functions derived from said frequency templates and used in a design method according to one embodiment of the invention; FIG. 10, a block diagram of a PLL of the type of FIG. 4a, "increased" weighting functions intended to reject the phase noise according to the templates of FIGS. 8 and 9; Fig. 11 is a condensed representation of the block diagram of Fig. 10; FIG. 12a, a block diagram of a PLL of the type of FIG. 4a, "augmented" with weighting functions for rejecting the phase noise and, in addition, imposing a constraint on the servo signal of FIG. VCO; FIG. 12b, a condensed representation of the block diagram of FIG. 12a; FIGS. 13a, 13b and 13c show the VCO phase noise transfer functions and the reference signal obtained using the weights of FIG. 12a, as well as the constraints that these transfer functions must respect; - Figure 13d, the Bode diagrams of these weights; FIGS. 14 and 15, the transfer functions of the correctors synthesized using the weights of FIG. 12a; FIGS. 16 to 19, various graphs illustrating the technical result of the invention; FIG. 20 is a block diagram of a circuit for determining an estimate of the phase noise of a signal; FIG. 21, the diagram of a PLL of the type of FIG. 4b, using a circuit for determining an estimate of the phase noise of the reference signal according to FIG. 20; FIG. 22 an analog PID corrector that can be used in the PLL of FIG. 21; FIG. 23, the diagram of a PLL of the type of FIG. 5b, using a circuit for determining an estimate of the phase noise of the output signal according to FIG. 20; FIG. 24, the block diagram of a radio frequency reception chain comprising a PLL according to FIG. 23; FIG. 25, the block diagram of a PLL with three degrees of freedom using a second corrector in anticipation control mode and a third corrector in feedback mode; FIG. 26, the application of the present invention to an all-digital PLL; and - Figure 27, the block diagram of a PLL with five degrees of freedom. FIG. 1 shows the block diagram of an analog PLL, receiving at its input a reference signal sref = Vref-sin [cpref (t)]. The reference signal and the output signal of the PLL, suut = Vout .cos [y (t)] are supplied to the inputs of an MX mixer, which outputs the product: smxcx sinkpref (t)] - coskp (t)] 0 (sinkpref (t) -Ey (t)] - sinkpref (t) - (p (t)] It is assumed that (Pref (t) and (pu (t) are essentially phase ramps, which means that the reference and output signals deviate perfect sinusoids.
    [0004] A low-pass filter FPB removes the "high frequency" sinkpref (t) -Ey (t) component from sri- ,: at the output of the filter we thus obtain the signal su "sinkpref (t) -y (t) ]. Assuming (pref (t) - y (t) - which is normally the case in steady state - we can approach the sine with the arc, which gives: suc <(Pref (t) - (p (t In other words, the signal su is proportional to the instantaneous phase difference between the reference signal and the output signal.This signal drives a voltage controlled oscillator VCO, which generates the jumper output signal If the filter, or corrector, FPB is appropriately sized, the VCO is slaved to the reference signal, i.e. (p (t) follows faithfully (Pref (t). a frequency divider block (shown in dashed line in FIG. 1, where N is the dividing factor) is introduced on the feedback path, between the output signal and the mixer, (p (t) will follow N (Pref ( t), thereby multiplying the frequency of the reference signal in the small signal regime (i.e., for (pref (t) .-- y (t)), the operation of the PLL can be illustrated by the diagram of Figure 2. This diagram should not be confused with a wiring diagram: 3025911 its 12 input and output signals are voltage values, but directly phases (pref and (p. The mixer is modeled by a phase comparator CMP, providing at its output a difference signal "c", and the VCO by a block having a transfer function G (s), typically an integrator. The low-pass filter, characterized by a transfer function F (s) and generating a servo signal "u", will be referred to in the following "corrector" to emphasize the fact that it performs other functions than the Low-pass filtering, such as loop stabilization, PLL synchronization, minimum bandwidth determination, and so on.
    [0005] The signal (pref can be considered as the useful signal on which the output (p of the PLL must be controlled.) The corrector must therefore ensure this servocontrol, however, the noise signals b and short are spurious signals - respectively the VCO and the oscillator generating the reference signal - which must be filtered in such a way that their contributions to the output of the PLL (p is as low as possible while guaranteeing enslavement. s) which guarantees these performance properties of the PLL will be called afterwards the PLL phase noise optimization Other sources of phase noise exist (phase comparator noise, frequency divider, etc.). ) but their contribution is usually less important PLL servo-control can be achieved via an analog or digital-type implementation, since the noise filtering requirement is naturally expressed As a template on the Spectral Power Density (DSP) of the signals, it is interesting to express the DSP of the output of the PLL with respect to the input signal DSPs considered. As a result, considering that the VCO noise, the noise of the reference and the reference signal are not correlated: 3025911 13 Sv (j24) 1 1+ GU27-tf) F (j27e) FUDge) G ( i271f) s _ef (j24) 1+ G (j2le) F (j2Tif) "2 Sb (i24) 2 S b'f j2Tif) + F (j21if) GU27-if 1+ G (j21-if) F (j27- if) (1) where S, is the DSP of the signal "x", with "x" being able to take the values: (Pref, b, in short, f the frequency expressed in Hz.
    [0006] Equation (1) highlights the square modules of the frequency responses of the transfer functions which connect the reference phase signal (pref and the phase noise of the reference, in short, and the VCO, b, with the output of the PLL The transfer function between the noise of the VCO, b, and the output of the PLL cp, will be denoted S (s) = 1 and will be called "function 1+ G (s) ns) 10 of sensitivity" . The transfer function between the phase noise of the short reference (or equivalent the phase signal of the reference (pref) and the output of the PLL will be denoted T (s) = G (s) F (s) and will be called "function of 1+ G (4F (s) additional sensitivity." (2) It is easy to realize that: 15 S (s) + T (s) = 1 + G (s) F (s) 1+ G (s) F (s) 1+ G (s) F (s) Generally the transfer function S is that of a high pass filter in order to be able to filter the contribution of the noise of the VCO around the carrier frequency of Therefore, in view of relation (2), the transfer function T represents a low-pass filter, which is responsible for shaping the short reference noise. because of the relation (2), and whatever the corrector F (s) chosen ensuring the stability of the PLL, it is not possible for a given frequency that the modules of the frequency responses of two transfer functions S (s) ) and T (s) are both weakly ieI (j22-e) "1 and ITUD-el" 1 for 25 f E Emin, fmaxi- If the frequency response module of the sensitivity function S (s) is low for a frequency given (S (j2 #) l "1), it is inevitable that the modulus of the frequency response of the complementary sensitivity function T (s) is close to 1 (TUD-gel -1) for the relation (2) is respected (see Fig. 3, where S and T are, respectively, a high-pass filter and a low-pass filter with the same cut-off pulse, co). Conversely, siIT (j22-tf1) then 1S (j2; zf1, -1. Thus, the relation (2) implies a fundamental limitation of the performances of a PLL according to the prior art in terms of phase noise filtering. Indeed, if the modules of the transfer functions S and T can not be weak at the same frequency or in the same frequency range, it is not possible to filter the two sources of noise b and at the same time At this frequency or in this frequency range, this limitation is inherent to the structure of the closed loop with a degree of freedom shown in FIGS. 1 and 2, and makes it necessary to accept a compromise favoring the filtering of a noise source. The invention makes it possible to overcome this fundamental limitation by introducing at least one additional degree of freedom into the servocontrol of the VCO, which makes it possible to control and optimize separately the constraints with respect to each of the co-operators. Therefore, it is important to ensure that the two transfer functions connecting the phase noise sources with the output of the PLL can have low gain frequency responses at the same time over a certain frequency range in order to perform noise filtering. FIG. 4a illustrates a first embodiment of the invention which differs from that of FIG. 2 in the presence, in addition to the corrector F1, arranged between the phase comparator and the VCO (hereinafter referred to as the "first corrector"). ), a second corrector F2 connected in advance control mode ("feed-forward" in English), receiving at its input the noisy phase of the reference signal: r = yref + brief. The output signals of the two correctors (correction signals) are summed by an adder node NA to provide the servocontrol signal of the VCO, u. More generally, the correction signals can be combined - linearly or not - to provide the servo signal u. In this embodiment, the first corrector F1 acts on both the noise of the VCO and on the noise of the reference, while the second corrector F2 acts specifically on the noise of the reference.
    [0007] FIG. 5a illustrates a second embodiment of the invention which differs from that of FIG. 4a in that the second corrector is connected in feedback mode ("feedback"), receiving at its input the signal In this embodiment, the first corrector F1 acts on both the noise of the VCO and on the noise of the reference, whereas the second corrector F2 acts specifically on the noise of the VCO. however, it is difficult to make PLLs based on these two schematic diagrams since it is difficult in practice to directly measure the phase noise signal at the input of the corrector F2 (s), since the signal "r" appears 4a and 5a is not, in fact, measurable in an electronic circuit, for this reason it is generally preferable to use an additional circuit which receives as input a noisy periodic voltage signal and provides at its output an estimate of the phase noise affecting this signal (for an embodiment of such a circuit, see FIG. 20 and the corresponding part of the description). This estimate of the phase noise can be advantageously used at the input of the second corrector F2 (s), as illustrated in FIGS. 4b (for the case of a connection in advance control) and 5b (for the case of a connection in feedback).
    [0008] It is also possible to combine anticipation control and feedback to achieve a PLL with three degrees of freedom; such a PLL will be described later with reference to FIG. 25. It is also possible to make phase-lock loops with more than three degrees of freedom to correct other sources of noise than the reference signal and the VCO. for example the noise introduced by a frequency divider. By way of example, FIG. 27 illustrates the block diagram of a PLL with five degrees of freedom comprising, in addition to the corrections F1 and F2 already present in the PLL with two degrees of freedom of FIG. 4b, a third corrector F3, a fourth corrector F4 and a fifth corrector F5. These additional degrees of freedom make it possible to reject, in addition to the noise of the VCO and the reference, the noise of the comparator 5 bcmp, that of the frequency divider DIV, bcilv and the total noise introduced by the filters, bu. The invention also proposes a systematic method for designing (synthesis of the transfer functions) of the correctors which will be described in detail below, with the aid of FIGS. 6a to 19. This method uses the "H .." method ( or "H-infinity"), known from the prior art, for satisfying a constraint on the output phase noise expressed by a DSP template of said phase noise - and possibly one or more other constraints - given an oscillator reference and a frequency-controlled oscillator with their own performance in terms of phase noise, also expressed by DSP templates. Advantageously, this method is implemented by computer, which means that at least one of its steps is implemented using a computer. The use of such a systematic method of design is all the more necessary as the number of degrees of freedom of the PLL is high. Without a systematic approach, the sizing of the five correctors of the PLL of Figure 27, for example, would be extremely complex. The systematic method of transfer functions of the correctors will be presented in the case of a PLL with two degrees of freedom, but can be easily generalized. A general introduction to the Ho method and to the use of weighting functions within this method - which is an important aspect of the invention - can be found in the following document: [Bib-1992], [ScF-2009] and [SkP-2005]. In addition to guaranteeing predefined performances in terms of rejection of the phase noise, the correctors must advantageously ensure that the output signal (p follows the signal (pref at the input, and that therefore the error signal c tends to zero when the time goes to infinity According to the theorem of the final value assuming that the PLL is stable, the correctors must ensure: limt, +, ', E (t) = liMs, 0 .SE (S) = liMs, 0 sS (s) cp'f (s) = 0 (3) We consider the case of a reference signal in the form of a phase ramp (the short voltage signal is therefore a sinusoid); Laplace is (pref (s) = As-2, where A is the slope of the ramp, so we get: limp, 0 sS (s) cp 'f (s) = linrS (s) As-2 = limAs - 1 S (s) = 0 (3 ') ps, from which it is deduced that the sensitivity function must have a slope of at least + 40dB / dec for low frequencies. frequency is requested and not in frequency Ince and in phase, one must only ensure that c tends to a constant value, possibly different from zero. In this case, the condition can be relaxed on the low frequency sensitivity function slope, which should only be greater than or equal to + 40dB / dec. In addition, it is desired to impose that the DSP phase noise output (Figure 7) respects a "template" imposed by the specifications defined by the borders represented by the hatching; in other words, the output phase noise DSP must be below these boundaries; Since the template is not defined for all the frequencies, it is advantageously replaced by the continuous function L, p (f). These output constraints must be respected taking into account the intrinsic performances of the components at the phase noise of the reference oscillator, Lbref (f) (FIG. 6a), and that of the controlled frequency oscillator Lb (f ) (Figure 6b), which are provided by the technical specifications of these components. From the DSP templates Lq (f), Lbref (f) and Lb (f), the templates for the frequency response modules of the two transfer functions, represented by solid lines in FIG. 8: L are determined ( p (f) / Lbref (f) - that is the stress on IS (j2-rrf) 1 (curve 80) - and L, p (f) / 1-13 (f) - that is i.e. the stress on IT (j2Trf) 1 (curve 82).
    [0009] 302 591 1 18 According to the method, the constraints on the modules of the frequency responses of the transfer functions S (s) and T (s) expressed by these templates are modeled by transfer functions called "weights". In the case of a system such as that of the invention, there are two kinds of weights: those in Wi input and those in output Wo. The weights can be chosen as whitening filters, in which case Wi is the inverse of the input noise DSP characteristic and Wo is the inverse of the output noise DSP characteristic. More generally, we consider the case of a generic transfer function H (s), whose modulus squared of the frequency response must respect the constraints imposed by the input and output noise DSP masks Lin (f) and Lout (f). One writes then: IH (j2Trf) 124Wo (j2-rrf) Wi (j2Trf) 1-1) 2 = Lout (f) / Lin (f) from where: 1W0 (j2-rrf) H (j2-rrf) Wi (j2Trf) 1 <1.
    [0010] In the case of the PLL of FIG. 4a, it is possible to use three weighting functions: two input (Wb and W) and one output (W, p), in short, such that: 1W (pWb1-1 approaches the constraint on IS (j2Trf) 1 and IWyWbref11 approaches the constraint on IT (j2Trf) 1. In reality, since the constraints have a complex shape, this approach would lead to high order controllers 20. It is therefore preferable to replace the original constraints (continuous lines in FIG. 8), obtained from the specifications (FIG. 7) and the technical specifications of the components (FIGS. 6a and 6b), by simplified, stronger constraints (lower than the constraints of FIG. origin at all frequencies), having a limited number (one or two, or even three, but preferably not more) of slope changes and asymptotic slopes of ± 20 dB / dec, or ± 40 dB / dec, or even ± 60 dB / dec, and preferably not more. The simplified constraint 81 on L, p (f) / Lb (f) - and thus on the sensitivity function S (s) - has a slope of +40, which is shown in dotted lines in FIG. dB / decade between 102 and 106 Hz, so as to ensure that the phase error c tends to zero in steady state (below 102 Hz the slope of the frequency response module of the sensitivity function n ' more important because this module is extremely small, of the order of -100 dB). Curve 83 represents the simplified constraint on IT (j2Trf) 1. Note also that the 5 cut-off frequencies for the attenuation of the two types of noise (attenuation greater than 6dB simultaneously for the two functions) are located more than two decades apart (107 Hz for the VCO noise, less than 105 Hz for the noise of the reference), while they are close or coincident in the case of an architecture with 1 degree of freedom.
    [0011] Alternatively, it is possible to use the phase error E to impose the performance constraints on the phase noise. This leads to constraining the DSP of the error c with respect to that of two noise signals (reference and VCO) using an equivalent constraint on LE / Lbref (the stress on LE / Lb is the same as that on L, p / Lb). In this case also it will be convenient to simplify the constraints. Figure 9 illustrates the simplified constraints on L, p / Lb = 1 '/ Lb (91), on 4 / Lbref (93) and on LE / Lbref (95). FIG. 10 illustrates the "augmented" system constituted by the phase-locked loop of FIG. 4a and its input weighting functions, Wb (s) and Wbref (s) and at the output W, p (s) and Ws ( s). In fact, only one of these two output weightings (at choice) is used for the synthesis of the correctors (the form of the input weighting functions depends on this choice). Two constituent parts of this augmented system can be distinguished: the (vector) corrector F (s), comprising the two correctors F1 and F2 to be synthesized and the adder node combining their outputs to generate the servo signal u, and a part so-called "augmented plant" (English) P (s), including all the other elements. Input signals v1 and v2 (which are transformed into b and short noises) and output signals z1 and z2 (obtained by weighting y and c, respectively) are, by construction weighting functions, white noise. . Figure 11 shows a condensed representation of the augmented system.
    [0012] The transfer function P (s) is given because it depends on the topology of the PLL and G (s), as well as the weights which have been determined in order to satisfy the constraints on the noise. phase. The transfer function F (s) is synthesized according to the method Ho., So as to satisfy the condition IIP (s) * F (s) II, ', <1 (4) where the operator "*" indicates the product of Redheffer and 11.11 ,, indicates the standard H. The search for a vector transfer function F (s) satisfying the inequality (4) is a classic problem that can be solved, by means of a computer, by numerical calculation algorithms well known in the prior art; see for example [ScF-2009]. According to the invention, the synthesis of the correctors may be subject to other constraints, for example: robust stability, which imposes IS (j2-rrf) IdB <6 dB Vf; 15 - limitation of the DSP of the control signal, or command, u (t). For the choice of weights to satisfy these constraints we can refer to [ScF-2009]. FIGS. 12a and 12b illustrate, in complete representation 20 and condensed respectively, the augmented system obtained if it is desired to comply with both a phase noise mask at the output (which is obtained by using the phase error c) and a DSP mask of the servo signal u. In FIG. 13a, curve 130 represents the simplified VCO noise attenuation constraint (4 / Lb), curve 131 modulates the frequency response of the complementary sensitivity function actually obtained, IT (j2Trf) 1, the curve 132 the simplified noise attenuation constraint of the reference (1-0-brief) and the curve 133 the modulus of the frequency response of the sensitivity function actually obtained, IS (j2Trf) 1. Note that the constraints are respected (the curve 131 and 133 are below the respective constraints 130 and 132). In addition, the maximum value of stress 130 does not exceed 6 dB, which implies robust stability. In FIG. 13b, the curve 134 represents a constraint on the relation between the noise of the reference and the control signal u, and the curve 135 the modulus of the frequency response of the transfer function between brief and u actually obtained. Similarly, in FIG. 13c, the curve 136 represents a constraint on the relationship between the noise of the VCO and the control signal u, and the curve 137 the modulus of the frequency response of the transfer function between b and u effectively. By applying this method of synthesis of the correctors to a particular case of specifications and for the topology of FIG. 4a, the following weightings are obtained: 0.04 s + 3350 Wb'f (s) = '(5) s + 1 Wb (s) = 10-6s2 + 2.10-3s +1 (6) Wu (S) = 2.10-3 (7) We (s) = 1 (8) The corresponding Bode diagrams are shown in the figure 13d (upper panel: module, lower panel: phase). Although these weightings have an order no greater than 2 (they correspond to simplified constraints), they nonetheless lead to transfer functions of the significant order correctors; the curves 140 and 141 in FIG. 14 respectively show the module and the phase of Fi (s), the curves 150 and 151 in FIG. 15 respectively show the module and the phase of F2 (s). These transfer functions can be simplified by removing the poles and zeros outside the frequency band of interest. The following transfer functions are thus obtained, the modules and phases of which are also shown in FIGS. 14 and 15 (curve 142: module of F1 after simplification, curve 143: phase of F1 after simplification, curve 152: 6. 14 s2 + 1.2 io-4 s + 6 4 302 5 9 1 1 22 module of F2 after simplification, curve 153: phase of F2 after simplification). The transfer functions of the simplified correctors are: Fi (s) = - 1'41 s + 1723.106 s +6732.104 5 F2 (s) = 1.5538s +1658.106 S Figure 16 represents the Bode diagrams of the amplitudes F1 (curve 160 ), of F2 (curve 162), the noise of the reference formatted by the correctors of the PLL with two degrees of freedom (curve 164) and the noise of the reference formatted by the single corrector of a PLL to 10 a degree of freedom dimensioned in a conventional manner so as to reject the reference noise (curve 166), as well as the noise of the VCO shaped by the corrector F1 of the PLL with two degrees of freedom or by the single corrector of the PLL at one degree of freedom (curve 168 - for the noise of the VCO, there is no difference.
    [0013] Curves 164, 166 and 168 are also enlarged in Figure 17 for clarity. Figure 18 illustrates the power spectral density of the output phase noise of the PLL with two degrees of freedom according to the invention (curve 180) compared to that of a PLL with a degree of freedom according to the prior art. Noise DSPs were estimated by the Welch method and are expressed in dBc, relative to the power of an ideal spectral line, without noise. FIG. 19 presents, by way of illustration, the results of electrical simulation of the performances of a PLL with two degrees of freedom exhibiting the two correctors thus synthesized. The curves represent the phase noise of the reference and the VCO at the output of PLL in open or closed loop as well as their added contributions compared to the noise contributions of the whole of the PLL (curve 190: phase noise of the reference in FIG. open loop output, curve 191: phase noise of the closed loop output reference, curve 192: VCO phase noise at the open loop output, curve 193: VCO phase noise at the closed loop output; curve 194, substantially coincident with 191: sum of the contributions of the reference and the VCO, curve 195: total phase noise at the output). The operating band of the PLL, BF, ranges between about 25 and 250 kHZ; the total phase noise is approximately constant within this band, between -113 and -115 dB. Once the correctors are synthesized by the method described above, the design of the PLL can be finalized, and then the PLL can be made in integrated or discrete form by conventional electronic techniques. As mentioned above, it is difficult to directly measure the phase noise signal of the PLL reference or output which must be supplied to the input of the corrector F2 (s). For this reason, it is advantageously provided to use an estimator circuit, adapted to receive a voltage signal (reference signal, or output signal of the PLL) as input, and to provide the corrector F2 (s) with an estimate of the phase noise affecting this signal (see Figures 4b and 5b). FIG. 20 shows a block diagram of such a circuit, receiving as input a periodic signal V (t) and comprising: a first branch comprising a delay module, introducing a delay Td of the signal V (t); a second branch, connected in parallel with the first branch and including a phase shifter module, introducing a phase shift Sy of the signal V (t), with 8V WrefT d 7 1 -2 + 21rk, ke Z, (9) where coref is the periodic signal frequency - a MIX mixer configured to multiply the delayed signal VTd from the first branch and the phase-shifted signal V8, p from the second branch; and a low-pass type Frei (s) rejection filter receiving as input the Vrni output signal from said mixer and supplying at its output a VExT signal constituting the desired estimate of the phase noise affecting the input signal V.
    [0014] From the formal point of view, the following demonstration presents the operation of the phase noise estimator. It is considered that the input signal V (t) is a coref pulsing sinusoid affected by a short phase noise (t) V (t) = A sin (wreft + short (t)). : V Td (t) = A sin (w'f x (t -Td) + b'f (t -Td)) V gco (t) = A sin (weft + b'f (t) - Sv) ( 12) Trigonometric calculations show that: 2 Vn, '(t) = -A [cos (2co, eft-co, efTd + b'f (t -) + b'f (t) - (50 + 2 (13) + cos (b'f (t -Td) -b'f (t) + 5q) -corefTd)] The Vmix component at the 2Wref pulse is intended to be filtered by the Frei filter; the relation (9) makes it possible to simplify the expression (13), so we can write A2 Vmix (t) = -2 sin (b'f (t-Td) bru (t)) VmixHF (t) (14) A2 -2 (b'f (t - Td) - brief (t)) + VmixHF (t) where VmixHF (t) is the high frequency component of Vmix which is filtered. In frequency representation, and neglecting the component VmixHF (t), we can write Vmix (s) -2 (1- ed) short (s) = H (s) brief (s) (15) For the output signal of the circuit to provide a image of the phase noise, the Frei filter would have to reverse the transfer function H (s); This is not possible because H (s) is non-causal, but the inversion can be performed on a limited band, or H (s) can be linearized: H (s) 4 Hun (s) = Tes (16) We can therefore take 5 Frei = x 1 (17). where K is a low frequency gain and t is a time constant. The rejector filter is therefore a low-pass filter, which had previously been admitted. Alternatively, H (s) can be integrated into the enhanced method P (s); in this case, it is taken into account during the synthesis of the correctors. In other words, the filter Frej can be "integrated" with one of the correctors of the PLL, in which case the phase noise estimation circuit can comprise only the delay module Td, the phase shifter module Sy and the MIX mixer.
    [0015] The hardware realization of the delay and phase shifter modules may depend on the considered PLL topology (see below). FIG. 21 shows the block diagram of a PLL with two degrees of freedom in anticipation control mode with estimation of the noise of the reference, of the type of FIG. 4b. In this configuration, the noise estimator circuit receives as input the reference signal, which is generated here by an OREF crystal oscillator. The feedback path of the loop comprises a DIV frequency divider; thus, the output signal of the PLL has a frequency that is a multiple of that of the reference signal. The phase shift and the delay can be introduced by amplifiers loaded by RC lines and followed by voltage comparator circuits, taking into account that a delay is represented by a phase shift which varies linearly with the frequency. The filter Frej and the correctors F1 and F2 can be realized, for example, in the form of correctors PID (Proportional - Integral 30 Derivative) with operational amplifiers, as illustrated in FIG. 22.
    [0016] FIG. 23 shows the block diagram of a PLL with two degrees of freedom in feedback modality with VCO noise estimation, of the type of FIG. 5b. This configuration, in which the noise estimator circuit is arranged downstream of the VCO, simplifies the production of the delay and phase shift modules. Thus, the phase shift ρ can be achieved by using a quadrature VCO (QVCO) well known to those skilled in the art if & p = Tc / 2; More generally, a polyphase filter can make it possible to generate an arbitrary phase shift φ. It is also possible to use a coupled oscillator system. By controlling the coupling ratio of the oscillators it is thus possible to adjust the advance or delay of one with respect to the other and to generate a controlled phase shift. The delay Td can be realized digitally in the case of oscillator VCO ring ("ring oscillator"). In the case of sinusoidal signals, the delay Td may be introduced by an LC propagation line or the like, for example a slow wave propagation line. An alternative suboptimal solution consists in replacing the delay Td by a phase shift SyR = covco.Td where wvco is the pulsation of the steady-state VCO. The solution is suboptimal insofar as the equivalent delay thus generated is not constant over all the frequencies around covco.
    [0017] Finally, the mixer can be made by NOR or XNOR logic gates or a Gilbert cell. Figure 25 shows the block diagram of a PLL with three degrees of freedom combining anticipation control (corrector F2) and feedback (corrector F'2) with estimation of the noise of the reference and the noise 25 of the VCO. The delay, phase shift, mixer and rejector filters of the phase estimator used to estimate the noise of the VCO are identified by the references Td ', MIX' and Frei 'to distinguish them from the corresponding elements of the estimator. phase of the reference. FIG. 24 shows the block diagram of a radio frequency reception channel using a two-degree-of-freedom PLL using a 23-type PLL as a local oscillator for the conversion to a radio frequency band. base, or intermediate frequency, the radiofrequency signal picked up by an ANT antenna and preamplified by a LNA low noise amplifier. Advantageously, the radiofrequency mixer MRF is used as a mixer of the noise estimation circuit, which makes it possible to economize an element. The local oscillator oscillates at the carrier frequency fo; the output of this oscillator is multiplied, by the mixer, by a part of itself which comes from a voluntary "leakage" through the delay module Td (represented by an arrow in the figure), which generates a signal at the frequency 2f0, which is filtered by the corrector F2, and a baseband signal, which is the feedback signal of the PLL. The low-pass filter Frei is not shown in the diagram of Figure 24 because it is integrated in the corrector F2. The invention is not limited to the case of an analog PLL, but may also relate to a digital PLL, and in particular an entirely digital PLL 15 (ADPLL "All-Digital PLL") as described in the articles [STA-2004]. ] and [STA-2005], as shown in Fig. 26. In this ADPLL, a digitally controlled oscillator DCO generates a CKV signal which is to be phase locked to a lower frequency reference signal, FREF. The ratio between the frequency of the COD and that of the reference is not necessarily complete; it is therefore necessary to generate a re-timed reference signal CKR, used as a clock signal. This CKR signal is obtained by oversampling FREF by the high frequency signal CKV using an ECH1 flip-flop. An APO accumulator counts the rising (or falling) edges of the CKV signal; the counting signal thus obtained, indicated by Rv [i], is re-timed at the rate of the clock signal CKR by means of a flip-flop ECH2; the signal re-timed is indicated by Rv [k]. The signal RR [k] is obtained by accumulating, with the aid of an accumulator APR, a binary word FCW equal to the ratio between the frequencies of CKV and FREF. The signal e [k] is obtained using a digital time converter ("Time-to-Digital Converter") TDC quantifying the time lag between the rising (or falling) edges of the FREF signals. and CKV, the output of which is re-timed at the rate of the clock signal CKR by means of a flip-flop ECH3. An estimate OE [k] of the phase error between FREF and CKV 5 is given by: OE [k] = RR [k] - Rv [k] + e [k] (1 8) It should be noted that, in this context, the "phase" of a signal is given by the number of its rising (or falling) fronts, counted from an initial moment.
    [0018] The error signal 4E [k] is inputted to a first transfer function corrector Fi (z). According to the invention, the ADPLL also comprises a second corrector in anticipation control mode, F2 (z), receiving as input the signal e [k], and / or a third corrector in feedback mode, F3 (z) , receiving as input the signal Rv [k].
    [0019] As in an analog embodiment, the control signals generated by the correctors Fi (z), F2 (z) and / or F3 (z) are combined in an adder node NA to obtain a control (digital) signal of the DCO oscillator.
    [0020] References [Bib-1992] Johen E. Bibel, Stephen Malyevac "Guidelines for the selection of weighting functions for H-infinity control", AD-A251 781 Naval Surface Warfare Center, Jan. 1992, URL: 25 http://www.dtic.mil/dtic/tr/fulltext/u2/a251781.pdf. [ScF-2009] Scorletti G. Fromion V. "Advanced Frequency Automatic", Course Polycopies, Engineering Sciences, http://cel.archivesouvertes.fr/ce1-00423848. [SkP-2005] S. Skogestad and I. Postlethwaite, "Multivariate Feedback Control, Analysis and Design", John Wiley and Chischester Sons, 2005. 3025911 29 [ChM-2007] Chaivipas W., A. Matsuzawa, "Analysis and Design. Design of Direct Reference Feed-Forward. Compensation for Fast-Settling All-Digital Phase-Locked Loop ". IEICE TRANS. ELECTRON., VOL.E90-C, NO.4 April 2007 5 [SNI-2012] B. Indu Rani, CK Aravind G. Ilango Saravan, C. Nagamani, "A three phase PLL with a dynamic feed forward frequency estimator for synchronization of grid connected converters under wide frequency variations ". Electrical Power and Energy Systems, 41: 63-70, 2012. [STA-2004] RBStaszewski et al., "All-Digital TX Frequency 10 Synthesizer and Discrete-time Receiver for Bluetooth Radio in 130-nm CMOS", IEEE Journal of Solid-State Circuits, Vol.39, No.12, Dec.2004 [STA-2005] RBStaszewski, PT Balsara "Phase-Domain All-Digital Phase-Locked Loop", IEEE Transaction on Circuits and Systems II: Express Briefs , Flight. 52, No. 3, March 2005. 15
    权利要求:
    Claims (16)
    [0001]
    REVENDICATIONS1. A method of designing a phase locked loop, of the type comprising; a controlled frequency oscillator (VCO, COD); a phase comparator (CMP) configured to determine a phase difference between an output signal of said controlled frequency oscillator and a reference signal; a corrector (Fi), said first corrector, configured to receive at the input a signal representative of said phase difference and to generate at its output a signal called said first correction signal; at least one other corrector (F2), said second corrector, configured to receive as input a signal representative of or affected by a phase noise of said reference signal or of said output signal of said controlled frequency oscillator and to generate at its output a signal said second correction signal; and - means (NA) for generating a servo signal (u) of said controlled frequency oscillator from said first and second correction signals; Said method comprising a step of determining transfer functions of said correctors and being characterized in that said step is implemented, by means of a computer, by applying method H_ using: - at input, a function of weighting (Wb) of a phase noise of said controlled frequency oscillator, said first weighting function, and a weighting function (W short) of a phase noise of a, - short / reference signal, said second weighting function, determined from nominal power spectral densities of said noise; and at the output, at least one weighting function (W, p, Ws) of a phase noise of an output signal of the phase-locked loop or a tracking error of said reference signal, so-called third weighting function, determined from a phase noise power spectral density mask of said output signal to be complied with.
    [0002]
    The method of claim 1 wherein said step of determining transfer functions of said correctors comprises the following substeps: a) determining a nominal power spectral density of said reference signal; b) determining a nominal power spectral density of the phase noise of said controlled frequency oscillator; c) determining a phase noise power spectral density mask of said output signal to be complied with; d) from said nominal power spectral densities and said power spectral density mask, determining at least said first, second and third weighting functions; e) construct an augmented system of said weights; and f) applying the method H_ to said augmented system to synthesize the transfer functions of said correctors. 20
    [0003]
    3. The method according to claim 2, wherein said step d) also comprises the determination of an output weighting function, called the fourth weighting function (Wu), of the power spectral density of said servocontrol signal from a power spectral density mask of said servo signal to be complied with. 25
    [0004]
    4. Method according to one of claims 2 or 3, also comprising a sub-step d) simplifying the weighting functions determined in sub-step d), the weighting functions thus simplified being used in the said sub-step d) step e), said simplification being implemented by approximating said weighting functions with lower order transfer functions and lower module 3025911 at least over a spectral range of operation of the latch-lock loop. phase.
    [0005]
    5. Method according to one of claims 2 to 4 also comprising a sub-step g) of simplifying the transfer functions synthesized during said substep f), said simplification being implemented by approaching said transfer functions by lower order transfer functions.
    [0006]
    6. Method according to one of claims 2 to 5 wherein said step f) is implemented with an additional constraint, wherein the module of the transfer function (S) between said output signal of said frequency controlled oscillator and said reference signal has, in at least one spectral range, a slope greater than or equal to +20 dB / decade and preferably 40 dB / decade.
    [0007]
    7. Method according to one of the preceding claims, wherein said phase-locked loop comprises at least one other corrector (F3), said third corrector, configured to receive as input a signal representative of or affected by a phase noise generated. within said loop, other than said phase noise of said output signal of said controlled frequency oscillator, and for generating at its output a signal said third correction signal, said means for generating a servocontrol signal of said frequency controlled oscillator being configured to generate said servo signal also from said third correction signal. said step of determining transfer functions of said correctors, implemented by said method Ho., also using a weighting function of said phase noise other than said phase noise of said output signal of said controlled frequency oscillator, also determined from the spectral power density of said noise. 3025911 33
    [0008]
    8. A method of manufacturing a phase locked loop, of the type comprising; - a controlled frequency oscillator (VCO); a phase comparator (CMP) for determining a phase difference between an output signal of said controlled frequency oscillator and a reference signal; a corrector (F1), said first corrector, configured to receive as input a signal representative of said phase difference and to generate at its output a signal called said first correction signal; At least one other corrector (F2), said second corrector, configured to receive as input a signal representative of or affected by a phase noise of said reference signal or of said output signal of said controlled frequency oscillator and to generate at its outputting a signal said second correction signal; and means (NA) for generating a servo signal (su, u) for controlling said frequency-controlled oscillator from said first and second correction signals; said method comprising: - a step of designing said phase locked loop; and a step of physical realization of the phase-locked loop thus conceived; characterized in that said designing step is carried out by a method according to one of the preceding claims. 25
    [0009]
    The method according to claim 8, wherein said phase-locked loop comprises at least one other corrector (F3), said third corrector, configured to receive as input a signal representative of or affected by a phase noise generated at the within said loop, other than said phase noise of said output signal of said controlled frequency oscillator, and for generating at its output a signal said third correction signal, said means for generating a servo signal of said 3025911 A controlled frequency oscillator being configured to generate said servo signal also from said third correction signal. said design step being carried out by a method according to claim 7. 5
    [0010]
    A phase locked loop comprising: - a controlled frequency oscillator (VCO); a phase comparator (CMP) for determining a phase difference between an output signal of said controlled frequency oscillator and a reference signal; a corrector (F1), said first corrector, configured to receive as input a signal representative of said phase difference and to generate at its output a signal called said first correction signal; at least one other corrector (F2), said second corrector, configured to receive as input a signal representative of or affected by a phase noise of said reference signal or of said output signal of said controlled frequency oscillator and to generate at its outputting a signal said second correction signal; and - means (NA) for generating a servo signal (su, u) for controlling said frequency-controlled oscillator from said first and second correction signals; characterized in that said first and second corrector have non-constant transfer functions, chosen so as to allow the rejection, in the same frequency band, of the phase noise of said reference signal and of the phase noise of said output signal said frequency controlled oscillator.
    [0011]
    The phase locked loop of claim 10 wherein said second corrector is configured to receive as input: a signal representative of the phase of said reference signal; 3025911 - an estimate of the phase noise of said reference signal.
    [0012]
    The phase locked loop of claim 11 further comprising a circuit for determining an estimate of the phase noise of said reference signal comprising: a delay module configured to generate a delayed version of a time T d of said signal reference ; a phase shifter module, configured to generate a version 10 of said reference signal having a phase shift,, with - CO CO T T----,,,,,,,,,,,,,,,,,,,,,,,,, where f f core core core core core où où où où où où où où où où où où où où où où; and - a mixer (MIX) configured to input the output signals of said retarder and phase shifter modules and to output its product; said second corrector being configured to receive as input said estimate of the phase noise of said reference signal.
    [0013]
    The phase locked loop of claim 10 wherein said second corrector is configured to receive as input: either a signal representative of the phase of said output signal of said controlled frequency oscillator; or an estimate of the phase noise of said output signal of said controlled frequency oscillator. 25
    [0014]
    The phase locked loop of claim 13 further comprising a circuit for determining an estimate of the phase noise of said output signal comprising: a delay module configured to generate a delayed version of a time T d of said signal Release ; A phase shifter module, configured to generate a version of said output signal having a phase shift, avec, with-co o o o z z + + +,,,,, where c is the frequency of said output signal; and a mixer configured to receive as input the output signals of said retarder and phase shifter modules and to output its product; said second corrector being configured to receive as input said estimate of the phase noise of said output signal. 10
    [0015]
    15. Phase locked loop according to one of claims 10 to 14 also comprising at least one other corrector (F3, F4, F5), said third corrector, configured to receive at the input: a signal representative of or affected by a noise generating a phase within said loop, other than said phase noise of said output signal of said controlled frequency oscillator, and generating at its output a signal said third correction signal, said signal generating means servocontrolling said controlled frequency oscillator being configured to generate said servo signal also from said third correction signal. 20
    [0016]
    16. Radio frequency reception chain comprising: a radio frequency preamplifier (LNA); a mixer (MRF) configured to input an output signal of said radio frequency preamplifier and a sinusoidal frequency conversion signal, and to output an intermediate frequency signal; and - a circuit for generating said sinusoidal frequency conversion signal; wherein said generating circuit of said sinusoidal frequency conversion signal comprises a phase locked loop according to claim 14, or claim 15 when dependent on claim 14, using said mixer as a mixer of said circuit determining an estimate of the phase noise of said output signal, and an oscillator configured to generate said reference signal. 5
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    引用文献:
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1458667A|FR3025911B1|2014-09-15|2014-09-15|MULTI-FREQUENCY DEGREE PHASE LOCKING BUCKLE AND METHOD FOR DESIGNING AND MAKING SAME|
    FR1458667|2014-09-15|FR1458667A| FR3025911B1|2014-09-15|2014-09-15|MULTI-FREQUENCY DEGREE PHASE LOCKING BUCKLE AND METHOD FOR DESIGNING AND MAKING SAME|
    US14/853,247| US9602114B2|2014-09-15|2015-09-14|Phase-locked loop with multiple degrees of freedom and its design and fabrication method|
    EP15184996.5A| EP2996249B1|2014-09-15|2015-09-14|Phase-locking loop with multiple degrees of freedom and method for designing and manufacturing same|
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